DNN Accelerator Resilience
A current research project I’m leading within the Harvard Architecture, Circuits, and Compilers Group with the help of Abdulrahman Mahmoud. The project aims to develop a software framework for analyzing a DNN accelerator’s resilience to errors (particularly bit flips caused by soft errors). The project’s novel approach is to use dataflow loop nest analysis to understand how an erroneous value in the memory hierarchy will be reused at the software-visible output activation level.
